The future of national defense depends on resilient systems that can endure the harshest conditions and deliver without fail. As modern strategic deterrent systems and aerospace missions become more complex, the microelectronics at their core must be mission-ready, radiation-hardened, and built for operational continuity. At JRC, we deliver microelectronics that meet this challenge head-on, supporting strategic deterrence and national defense missions with unmatched reliability.
JRC engineers develop and deliver custom radiation-hardened semiconductor technology for mission-critical aerospace and defense applications. We specialize in:
Radiation effects like single-event upsets and latch-ups have long forced designers to rely on Triple Mode Redundancy (TMR), a method that triples circuit size, power use, and cost while still leaving blind spots in protection. When NASA’s High Performance Space Computer (HPSC) hit delays and mounting program risk with TMR, JRC’s LEAP Standard Cell Library changed the equation. By embedding radiation hardening directly into the cell itself, LEAP delivered 10× greater resilience with only a fraction of the size, power, and performance penalties, accelerating development, reducing cost, and enabling next-generation space processors once thought impossible.
Our Specialized Tools
Sec - 5Radiation-hardened, customizable, and mission tested
High-speed physics based software for radiation modeling.
Tailored for space-grade operations
We partner directly with government test facilities and labs to simulate mission conditions
- 01Complete 12nm standard cell library: 13K+ rad-hard cells for full digital logic coverage
- 02Rad-hard enablement baked in to the logic cell to reduce program risk
- 03Our logic cells allow your circuit designers to focus on the overall chip design instead of radiation mitigation designs that introduce program risk
- 04Accuro Tool Suite – Physics based, high-speed modeling reduces design risk and time-to-tapeout
- 05Custom Support Teams – We don’t just license IP, we engineer alongside you, providing full-cycle design, simulation, and radiation tested
- 06TCAD + EDA expertise that flattens the learning curve
- 07Accurate prediction of error rates for custom IP blocks
- 08Specialized flip-flop & SRAM cell design experience for space-grade builds trusted performance, used across NASA and spaceflight-critical program
- 09LEAP standard cells eliminate the need for Triple Mode Redundancy (TMR), delivering radiation-hard protection in a single cell rather than triplicates, saving significant power, performance, and area (PPA)
- 10Minimized design penalties unlike TMR, LEAP reduces overhead in power consumption and circuit area, enabling more efficient, compact, and reliable rad-hard designs
- 11Superior resilience at advanced nodes as processes shrink (Intel 18a, TSMC 2N, GAA, etc.), voting cells in TMR become too close and risk simultaneous failure. LEAP avoids this, providing reliable protection where TMR falters
- 1210^5× harder than commercial IP LEAP standard cells deliver unmatched hardness compared to commercial alternatives or legacy RHBD techniques
- 13Simplified design cycle circuit designers can focus on higher-level logic and system performance instead of managing TMR triplication and voting logic
- 14Better than alternative RHBD techniques (like DICE) while DICE offers some radiation tolerance, it cannot match the hardness, efficiency, or scalability of LEAP
- 15Trusted by the Missile Defense Agency, NASA, and the United States Navy
- 16Custom-built, tailored for modern foundries and defense integration
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