JRC’s Custom Design for Defense Operations closes this gap. We deliver radiation-hardened semiconductor solutions that are custom-engineered for reliability, power efficiency, and long-term durability in the most unforgiving operational environments.
JRC provides end-to-end design of radiation-hardened microelectronics, using our proprietary LEAP (Layout Design through Error Aware Positioning) methodology to ensure ultra-low Soft Error Rate (SER) and robust latch-up immunity. Using our proprietary LEAP methodology, we optimize circuit design to mitigate Soft Error Rate (SER) and latch-up sensitivity, ensuring unmatched performance and resilience in the most challenging operational environments
Core assets supporting this capability
Sec - 3Proprietary cell designs optimized for latch-up resistance and layout-based SER mitigation
Internal tools for radiation analysis & design software, simulating, validating, and hardening circuits
Defense-cleared engineers with deep expertise in radiation-hardened ASIC development
Secure facilities enabling rapid iteration and reliability qualification
- 01Develop custom designs or optimize your design to improve resilience, reliability, speed, and power
- 02Our advanced tool knowledge will shorten your design process and improve chip performance against radiation effects
- 03Radiation-Tested and Mission-Ready – Every solution is built to meet or exceed DOD radiation tolerance specs
- 04Proprietary LEAP Technology – Unique physics-based-based methodology not available anywhere else in the market
- 05Defense-Native Engineering – Every project is led by teams with real-world defense systems integration experience
- 06Seamless Modernization Integration – Designed to plug into current and next-gen deterrence platforms
